Compact Analytical Model of Dual Material Gate Tunneling Field Effect Transistor using Interband Tunneling and Channel Transport

In this paper, we have developed a 2-D analytical
model for surface potential and drain current for a long channel
dual material gate (DMG) silicon-on-insulator (SoI) tunneling
field-effect transistor (TFET). This model includes the effect
of drain voltage, gate metal work function, oxide thickness,
and silicon film thickness, without assuming a fully depleted
channel. The proposed model also includes the effect of charge
accumulation at the interface of the two gates and the variation
in the tunneling volume with the applied gate voltage. The
accuracy of the model is tested using 2-D numerical simulations.
In comparison with the conventional TFET, the proposed model
predicts that a DMGTFET provides a higher ON-state current
(ION), a better ON-state to OFF-state current (ION/IOFF) ratio,
and a better subthreshold slope.

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