Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET

In this paper, we propose a 2-D analytical model for surface potential and drain current for a long channel p-type gate-all-around nanowire tunneling field effect transistor with a circular cross section. This model includes the effect of drain voltage, gate metal work function, oxide thickness, and radius of the silicon nanowire without assuming a fully depleted channel. The proposed model also includes the effect of the variation in the tunneling volume with the applied gate voltage. The model is tested using 3-D numerical simulations and is found to be accurate for all gate voltages except for subthreshold region.

Download the paper from: http://web.iitd.ac.in/~mamidala/id11.htm

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