The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs

Abstract—The ground plane (GP) concept is one of the techniques used to  reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs  and is effective only when the distance between the GP and the drain is  small as compared with the channel length. Therefore, if the GP is placed  in the substrate (GPS), the buried oxide (BOX) thickness should be kept as  small as possible which, however, results in an increased subthreshold slope. As a result, for sub-100-nm channel lengths, it is not possible to  achieve both reduced DIBL and steep subthreshold slope using GPS. In  this brief, a new device structure with the GP BOX is proposed to  overcome the aforementioned shortcomings so that a reduced DIBL as  well as an improved subthreshold slope can be obtained. Two-dimensional  simulation is used to understand the efficacy of the proposed method.
Index Terms—Drain-induced barrier lowering (DIBL), ground plane (GP), short-channel effects (SCEs), silicon-on-insulator (SOI) MOSFET, subthreshold slope, 2-D simulation.

The above paper can be downloaded from

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