Poly-silicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET

We propose a new trench gate power MOSFET with poly-Si spacers  formed in the trench to work as gate material. This approach reduces the  total gate charge and gate-to-drain capacitive coupling without affecting any  other device performance parameter. Using 2-D numerical simulation on  a$sim$25-V trench gate MOSFET, we have shown that using a 50-nm- wide spacer gate in a $hbox{1} muhbox{m} times hbox{1} muhbox{m}$  trench may give $>$ 40% reduction in the gate-to-drain charge compared  with the conventional device. The proposed technique has been shown to  be better than the other techniques proposed earlier for reducing gate  charge as it does not affect the gate control of the accumulation region  charge or any other performance parameter, e.g., breakdown voltage, and  can be implemented along with any of the existing techniques.

This paper can be downloaded from http://web.iitd.ac.in/~mamidala/id11.htm



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