A comprehensive approach for modeling the threshold voltage of nanoscale strained silicon-on-insulator (SSOI) and strained Si-on-SiGe-on-insulator (SSGOI) MOSFETs is presented. The model includes the effect of strain in terms of Ge mole fraction and various other device parameters—channel length, channel doping, strained silicon ﬁlm thickness, gate oxide thickness and gate work function. The accuracy of the proposed threshold voltage model is veriﬁed using two-dimensional numerical simulations. We have also demonstrated that our model can accurately predict the DIBL effects.
Keywords Strained silicon · Silicon-on-insulator · MOSFET · Threshold voltage · Modeling and simulation
The above paper can be downloaded from http://web.iitd.ac.in/~mamidala/id11.htm