Compact Modeling of Parasitic Internal Fringe Capacitance Effects on the Threshold Voltage of High-K Gate Dielectric Nanoscale SOI MOSFETs,

Abstract—A compact model for the effect of the parasitic internal fringe  capacitance on the threshold voltage of high-k gatedielectric silicon-on- insulator MOSFETs is developed. The authors’ model includes the effects  of the gate-dielectric permittivity, spacer oxide permittivity, spacer width,  gate length, and the width of an MOS structure. A simple expression for the  parasitic internal fringe capacitance from the bottom edge of the gate  electrode is obtained and the charges induced in the source and drain  regions due to this capacitance are considered. The authors demonstrate  an increase in the surface potential along the channel due to these  charges, resulting in a decrease in the threshold voltage with an increase in  the gate-dielectric permittivity. The accuracy of the results obtained using  the authors’ analytical model is verified using two-dimensional device simulations.
Index Terms—High-k gate dielectric, insulated gate field effect transistors (FETs), internal fringe capacitance, silicon-oninsulator (SOI) MOSFET, threshold voltage, two-dimensional (2-D) modeling.

The above paper can be downloaded from http://web.iitd.ac.in/~mamidala/id11.htm

This entry was posted in Abstracts of my Research Work and tagged , , , , , . Bookmark the permalink.

I value your feedback. Please feel free to comment.

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s