A Simple Analytical Threshold Voltage Model of Nanoscale Fully Depleted Single-Layer Strained-Silicon-on-Insulator (SSOI) MOSFETs

Abstract—A grounded lamination gate (GLG) structure for high-κ gate- dielectric MOSFETs is proposed, with grounded metal plates in the spacer  oxide region. Two-dimensional device simulations performed on the new  structure demonstrate a significant improvement with respect to the threshold  voltage roll-off with increasing gate-dielectric constant (due to parasitic internal  fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.
Index Terms—High-κ gate dielectric, internal fringe capacitance, MOSFET, silicon-on-insulator (SOI), simulation, threshold voltage.

The above paper can be downloaded from http://web.iitd.ac.in/~mamidala/id11.htm

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