A New Grounded Lamination Gate (GLG) for Diminished Fringe Capacitance Effects in High-K Gate Dielectric MOSFETs

Abstract—For the first time, a simple and accurate analytical model for the  threshold voltage of nanoscale single-layer fully depleted strained-silicon- on-insulator MOSFETs is developed by solving the two-dimensional (2-D)  Poisson equation. In the proposed model, the authors have considered  several important parameters: 1) the effect of strain (in terms of equivalent  Ge mole fraction); 2) short-channel effects; 3) strained-silicon thin- film  doping; 4) strained-silicon thin-film thickness; and 5) gate work function and  other device parameters. The accuracy of the proposed analytical model is  verified by comparing the model results with the 2-D device simulations. It  has been demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film,  i.e., with increasing equivalent Ge concentration. The proposed compact model can be easily implemented in a circuit simulator.
Index Terms—MOSFET, nanoscale, short-channel effects, silicon-on-insulator (SOI), simulation, strain, threshold voltage, two-dimensional (2-D) modeling.

The above paper can be downloaded from http://web.iitd.ac.in/~mamidala/id11.htm

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