The authors report a new p-n-p surface accumulation layer transistor (SALTran) on SOI, which uses the concept of surface accumulation of holes near the emitter contact to signiﬁcantly improve the current gain. Using two-dimensional simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the previously published conventional p-n-p lateral bipolar transistor (LBT) structure. From the simulation results it is observed that, depending on the choice of the emitter doping and the emitter length, the proposed SALTran exhibits a current gain enhancement of around twenty times that of the compatible lateral bipolar transistor, without deteriorating the cutoff frequency. Reasons for the improved performance of the SALTran are discussed, based on these detailed simulation results.
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