Realizing high current gain PNP transistors using a novel Surface Accumulation Layer Transistor (SALTran) concept

The authors report a new p-n-p surface accumulation layer transistor  (SALTran) on SOI, which uses the concept of surface accumulation of  holes near the emitter contact to significantly improve the current gain.  Using two-dimensional simulation, the performance of the proposed  device has been evaluated in detail by comparing its characteristics with  those of the previously published conventional p-n-p lateral bipolar  transistor (LBT) structure. From the simulation results it is observed that,  depending on the choice of the emitter doping and the emitter length, the  proposed SALTran exhibits a current gain enhancement of around twenty  times that of the compatible lateral bipolar transistor, without deteriorating  the cutoff frequency. Reasons for the improved performance of the  SALTran are discussed, based on these detailed simulation results.

This paper can be downloaded from

This entry was posted in Abstracts of my Research Work and tagged , , , , , . Bookmark the permalink.

I value your feedback. Please feel free to comment.

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Google+ photo

You are commenting using your Google+ account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )


Connecting to %s