Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-on-Insulator Metal Oxide Field Effect Transistors due to Induced Back-Gate Step Potential

In this letter we discuss how the short channel behavior in sub 100 nm  channel range can be improved by inducing a step surface potential profile  at the back gate of an asymmetrical double gate (DG) silicon-on-insulator  (SOI) metal–oxide–semiconductor field-effect-transistor (MOSFET) in  which the front gate consists of two materials with different work functions.
KEYWORDS: drain induced barrier lowering (DIBL), double gate, dual material gate, gate-to-gate coupling, silicon-on-insulator, MOSFET

This paper can be downloaded from http://web.iitd.ac.in/~mamidala/id11.htm

This entry was posted in Abstracts of my Research Work and tagged , , , . Bookmark the permalink.

I value your feedback. Please feel free to comment.

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google+ photo

You are commenting using your Google+ account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )


Connecting to %s