Two-Dimensional Analytical Modeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET and Evidence for Diminished Short-Channel Effects

A two–dimensional (2-D) analytical model for the surface potential variation along the  channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain  and body doping concentrations, the lengths of the gate metals and their work functions,  applied drain and substrate biases, the thickness of the gate and buried oxide and also the  silicon thin film. We demonstrate that the surface potential in the channel region exhibits a  step function that ensures  the screening of the drain potential variation by the gate near the drain resulting in suppressed  SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended  to find an expression for the threshold voltage in the submicrometer regime, which predicts a  desirable “rollup” in the threshold voltage with decreasing channel lengths. The accuracy of the  results obtained using our analytical model is verified using 2-D numerical simulations.
Index Terms—Device scaling, insulated gate field effect transistors, short-channel effects (SCEs), silicon-on-insulator (SOI) MOSFET, threshold voltage, two-dimensional (2-D) modeling.

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