Estimation and Compensation of Process Induced Variations in Nanoscale Tunnel Field Effect Transistors (TFETs) for Improved Reliability

—Tunnel field-effect transistors (TFETs) have extremely low leakage current, exhibit excellent subthreshold swing, and are less susceptible to short-channel effects. However,  TFETs do face certain special challenges, particularly with respect to the process-induced  variations in the following: 1) the channel length and 2) the thickness of the silicon thin film  and gate oxide. This paper, for the first time, studies the impact of the aforementioned  process variations on the electrical characteristics of a double-gate tunnel field-effect  transistor (DGTFET). Using 2-D device simulations, we propose the strained DGTFET as a  possible solution for effectively compensating the process-induced variations in the ON-current, threshold voltage, and subthreshold swing and improving the reliability of the  DGTFET.

Index Terms—CMOS technology, process-induced variations, strain, tunnel field-effect transistor (TFET)

The complete paper can be downloaded from http://web.iitd.ac.in/~mamidala/id11.htm

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